1. Field of the Invention
The present invention relates to a circuit model extracting method, and more particularly, to a circuit model extracting method for representing output driving capability of an interface pin of an application circuit, and for representing an input capacitor of another interface pin of the application circuit.
2. Description of the Prior Arts
Generally speaking, in order to generate the liberty model of the circuit design hard block, two kinds of design information should be specified as follows: (1) the interface pin capacitance; and (2) the equivalent driving capability of the output pin.
The current processing ways for specifying the design information are divided into the following two types: (1) artificial trace: the devices, to which each pin is connected, are traced by manual operation for calculating the equivalent capacitance of the pin and tracing the equivalent driving capability of the output pin. However, this way involves much wasted time and manpower and has a high error probability of occurrence, for example, miss, error calculation, write error, etc.; and (2) simulation: the interface pin capacitance is obtained by dumping a DC simulation result to a pin capacitor of each of the pins under the single bias state. However, there is no way to ensure that the pin capacitor is at the worst case. The driving capability of the output pin is obtained by performing the transient simulation. The fixed load is first coupled to the output pin, and then the transition time of the output pin is recorded. After all buffers in a standard cell library are coupled to loads having the same value, the transition simulation is run for searching out the output transition time, and an indication is provided that the output driver is similar to the buffer if the output transition time is close to the transition time of the output pin. Although the interface pin in the prior art can obtain the approximate driving capability by performing the mentioned ways, the simulation may require a great deal of time to get the result as the complexity of the IC design increases. Furthermore, the designer needs to design one or more input patterns for obtaining the wanted result, resulting in much time consumption for preparing simulation environment.
Accordingly, in view of the above drawbacks, it is imperative that an apparatus and method are designed so as to solve the foregoing drawbacks.